B1.90 Interrupt Status Register
The ISR characteristics are:
Purpose
Shows whether an IRQ, FIQ, or external abort is pending. An indicated pending abort might be
a physical abort or a virtual abort.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Configurations
ISR is architecturally mapped to AArch64 register ISR_EL1. See B2.72 Interrupt Status
Register, EL1 on page B2-484.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ISR is a 32-bit register.
31 9 8 7 6 5
0
RES0FIA
RES0
Figure B1-44 ISR bit assignments
[31:9]
Reserved, RES0.
A, [8]
External abort pending bit:
0 No pending external abort.
1 An external abort is pending.
I, [7]
IRQ pending bit. Indicates whether an IRQ interrupt is pending:
0 No pending IRQ.
1 An IRQ interrupt is pending.
F, [6]
FIQ pending bit. Indicates whether an FIQ interrupt is pending:
0 No pending FIQ.
1 An FIQ interrupt is pending.
[5:0]
Reserved, RES0.
B1 AArch32 system registers
B1.90 Interrupt Status Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-299
Non-Confidential
To Next Page
Loading...
Need help?
General
