ARM Cortex-A35

To access the ISR:
MRC p15, 0, <Rt>, c12, c1, 1; Read ISR into Rt
Register access is encoded as follows:
Table B1-71 ISR access encoding
coproc opc1 CRn CRm opc2
1111 000 1100 0001 000
B1 AArch32 system registers
B1.90 Interrupt Status Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-300
Non-Confidential