B1.113 Translation Table Base Register 0
The TTBR0 characteristics are:
Purpose
Holds the base address of translation table 0, and information about the memory it occupies.
This is one of the translation tables for the stage 1 translation of memory accesses from modes
other than Hyp mode.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
Used in conjunction with the TTBCR. When the 64-bit TTBR0 format is used, cacheability and
shareability information is held in the TTBCR and not in TTBR0.
Configurations
TTBR0 (NS) is architecturally mapped to AArch64 register TTBR0_EL1. See
B2.97 Translation Table Base Register 0, EL1 on page B2-546.
TTBR0 (S) is mapped to AArch64 register TTBR0_EL3. See B2.99 Translation Table Base
Register 0, EL3 on page B2-550.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
Attributes
TTBR0 is:
• A 32-bit register when TTBCR.EAE is 0.
• A 64-bit register when TTBCR.EAE is 1.
There are different formats for this register. TTBCR.EAE determines which format of the register is
used.
B1 AArch32 system registers
B1.113 Translation Table Base Register 0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-346
Non-Confidential
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