ARM Cortex-A35 User Manual

B2.37 CPU Extended Control Register, EL1
The CPUECTLR_EL1 characteristics are:
Purpose
Provides additional IMPLEMENTATION DEFINED configuration and control options for the processor.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
The CPUECTLR_EL1 can be written dynamically.
The CPUECTLR_EL1 is write accessible in EL1 if ACTLR_EL3.CPUECTLR is 1 and
ACTLR_EL2.CPUECTLR is 1, or ACTLR_EL3.CPUECTLR is 1 and SCR.NS is 0.
The CPUECTLR_EL1 is write accessible in EL2 if ACTLR_EL3.CPUECTLR is 1.
Configurations
The CPUECTLR_EL1 is mapped to the AArch32 CPUECTLR register. See B1.43 CPU
Extended Control Register on page B1-212.
Attributes
CPUECTLR_EL1 is a 64-bit register.
7
6 5 3 2
RES0
063
SMPEN
FPRETCTL
CPURETCTL
Figure B2-12 CPUECTLR_EL1 bit assignments
[63:7]
Reserved, RES0.
SMPEN, [6]
Enable hardware management of data coherency with other cores in the cluster. The possible
values are:
0 Disables data coherency with other cores in the cluster. This is the reset value.
1 Enables data coherency with other cores in the cluster.
Set the SMPEN bit before enabling the caches, even if there is only one core in the system.
[5:3]
Advanced SIMD and floating-point retention control. The possible values are:
0b000 Disable the retention circuit. This is the reset value.
0b001 2 Architectural Timer ticks are required before retention entry.
0b010 8 Architectural Timer ticks are required before retention entry.
0b011 32 Architectural Timer ticks are required before retention entry.
B2 AArch64 system registers
B2.37 CPU Extended Control Register, EL1
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B2-416
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English