A8.1 About the AXI master interface
You can configure the processor to use the AXI protocol for the master memory interface.
Read responses
The AXI master can delay accepting a read data channel transfer by holding RREADY LOW for an
indeterminate number of cycles. RREADY can be deasserted LOW between read data channel transfers
that form part of the same transaction.
Write responses
The AXI master requires that the slave does not return a write response until it has received the write
address.
The AXI master always accepts write responses without delay by holding BREADY HIGH.
Barriers
You must ensure that your interconnect and any peripherals connected to it do not return a write response
for a transaction until that transaction would be considered complete by a later barrier. This means that
the write must be observable to all other masters in the system. Arm expects the majority of peripherals
to meet this requirement.
Related information
A8.2 AXI privilege information on page A8-107
A8 AXI Master Interface
A8.1 About the AXI master interface
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A8-106
Non-Confidential
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