ARM Cortex-A35 User Manual

B2.56 AArch32 Debug Feature Register 0, EL1
The ID_DFR0_EL1 characteristics are:
Purpose
Provides top level information about the debug system in AArch32.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_DFR0_EL1 is architecturally mapped to AArch32 register ID_DFR0. See B1.73 Debug
Feature Register 0 on page B1-267.
Attributes
ID_DFR0_EL1 is a 32-bit register.
31
12 11 8 7 0
RES0
4 324 23 20 19 16 1528 27
PerfMon MProfDbg MMapTrc CopTrc CopSDbg CopDbgReserved
Figure B2-29 ID_DFR0_EL1 bit assignments
[31:28]
Reserved, RES0.
PerfMon, [27:24]
Indicates support for performance monitor model:
0x3 Support for Performance Monitor Unit version 3 (PMUv3) system registers.
MProfDbg, [23:20]
Indicates support for memory-mapped debug model for M profile processors:
0x0 Processor does not support M profile Debug architecture.
MMapTrc, [19:16]
Indicates support for memory-mapped trace model:
0x0 ETM is not implemented.
0x1 Support for Arm trace architecture, with memory-mapped access.
In the Trace registers, the ETMIDR gives more information about the implementation.
CopTrc, [15:12]
Indicates support for coprocessor-based trace model:
0x0 Processor does not support Arm trace architecture with CP14 access.
[11:8]
Reserved, RES0.
CopSDbg, [7:4]
B2 AArch64 system registers
B2.56 AArch32 Debug Feature Register 0, EL1
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English