ARM Cortex-A35 User Manual

A9.4 ACE transactions
The processor generates only a subset of all possible ACE transactions on the ACE master interface.
The processor does not generate any FIXED bursts and all WRAP bursts fetch a complete cache line
starting with the critical word first. A burst does not cross a cache line boundary.
The cache linefill fetch length is always 64 bytes.
For WriteBack transfers the supported transfers are:
• WRAP 4 128-bit for read transfers (linefills).
• INCR 4 128-bit for write transfers (evictions).
• INCR N (N:1, 2, or 4) 128-bit write transfers (read allocate).
For Non-cacheable transactions:
• WRAP 4 128-bit for read transfers.
• INCR N (N:1, 2, or 4) 128-bit for write transfers.
• INCR N (N:1, 2, or 4) 128-bit for read transfers.
• INCR 1 32-bit, 64-bit, and 128-bit for read transfers.
• INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for write transfers.
• INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for exclusive write transfers.
• INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit for exclusive read transfers.
For Device transactions:
• INCR N (N:1, 2, or 4) 128-bit read transfers.
• INCR N (N:1, 2, or 4) 128-bit write transfers.
• INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit read transfers.
• INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit write transfers.
• INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit exclusive read transfers.
• INCR 1 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit exclusive write transfers.
External memory accesses generate the following transactions in an implementation configured with an
ACE master interface.
Table A9-4 ACE transactions
Attributes ACE transaction
Memory type Shareability Domain Load Store Load exclusive Store exclusive
Device - System ReadNoSnoop WriteNoSnoop
ReadNoSnoop and
ARLOCKM set to
HIGH
WriteNoSnoop and
AWLOCKM set to
HIGH
Normal, inner Non-
cacheable, outer Non-
cacheable
Non-shared System ReadNoSnoop WriteNoSnoop
ReadNoSnoop and
ARLOCKM set to
HIGH
WriteNoSnoop and
AWLOCKM set to
HIGH
Inner-shared
Outer-shared
A9 ACE Master Interface
A9.4 ACE transactions
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A9-117
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English