ARM Cortex-A35 User Manual

Table A9-4 ACE transactions (continued)
Attributes ACE transaction
Memory type Shareability Domain Load Store Load exclusive Store exclusive
Normal, inner Non-
cacheable, outer Write-
Back or Write-
Through, or Normal,
inner Write-Through,
outer Write-Back,
Write-Through or Non-
cacheable, or Normal
inner Write-Back outer
Non-cacheable or
Write-Through
Non-shared System ReadNoSnoop WriteNoSnoop
ReadNoSnoop ReadNoSnoop
Inner-shared System ReadNoSnoop WriteNoSnoop ReadNoSnoop with
ARLOCKM set to
HIGH
WriteNoSnoop with
ARLOCKM set to
HIGH
Outer-shared System
Normal, inner Write-
Back, outer Write-
Back
Non-shared Non-
shareable
ReadNoSnoop WriteNoSnoop
ReadNoSnoop WriteNoSnoop
Inner-shared Inner
Shareable
ReadShared ReadUnique or
CleanUnique if
required, then a
WriteBack when
the line is evicted
ReadShared with
ARLOCKM set to
HIGH
CleanUnique with
ARLOCKM set to
HIGH if required,
then a WriteBack
when the line is
evicted
Outer-shared Outer
Shareable
The following table shows the ACE transactions that can be generated, and some typical operations that
might cause the transactions to be generated. This is not an exhaustive list of ways to generate each type
of transaction, because there are many possibilities.
Table A9-5 ACE transactions and typical operations
Transaction Operation
ReadNoSnoop Non-cacheable loads or instruction fetches. Linefills of non-shareable cache lines into L1 or L2.
ReadOnce Cacheable loads that are not allocating into the cache, or cacheable instruction fetches when there is no L2
cache.
ReadClean Not used.
ReadNotSharedDirty Not used.
ReadShared L1 Data linefills started by a load instruction, or L2 linefills started by an instruction fetch.
ReadUnique L1 Data linefills started by a store instruction.
CleanUnique Store instructions that hit in the cache but the line is not in a unique coherence state. Store instructions that are
not allocating into the L1 or L2 caches, for example when streaming writes.
MakeUnique Store instructions of a full cache line of data, that miss in the caches, and are allocating into the L2 cache.
CleanShared Cache maintenance instructions.
CleanInvalid Cache maintenance instructions.
MakeInvalid Cache maintenance instructions.
DVM TLB and instruction cache maintenance instructions.
DVM complete DVM sync snoops received from the interconnect.
A9 ACE Master Interface
A9.4 ACE transactions
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A9-118
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English