ARM Cortex-A35 User Manual

A1.4 Supported standards and specifications
The Cortex‑A35 processor implements the Armv8-A architecture and some architecture extensions. It
also supports various interconnect, interrupt, timer, debug, and trace architectures.
Table A1-3 Compliance with standards and specifications
Architecture specification
or standard
Version Notes
Arm architecture
Armv8-A
• AArch64 and AArch32 execution states.
• All Exception levels in each execution state.
• A64, A32, and T32 instruction sets.
Arm architecture extensions • Advanced SIMD and floating-point
support
• Cryptographic Extension
• You cannot implement floating-point without
Advanced SIMD.
• You cannot implement the Cryptographic Extension
without the Advanced SIMD and floating-point
support.
Interconnect • AMBA 4 AXI
• AMBA 4 ACE
• AMBA 5 CHI
You can also connect the processor to an AMBA 3 AXI
interconnect.
Generic Interrupt Controller v4 -
Generic Timer Armv8-A -
PMU v3 -
Debug Armv8 -
CoreSight v2 -
Embedded Trace Macrocell ETMv4 -
Related information
Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile
Arm® AMBA® 5 CHI Protocol Specification
Arm® AMBA® AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite, ACE and ACE-Lite
Arm® Generic Interrupt Controller Architecture Specification
Arm® CoreSight™ Architecture Specification
Arm® ETM Architecture Specification, ETMv4
A1 Introduction
A1.4 Supported standards and specifications
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A1-34
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English