ARM Cortex-A35 User Manual

B1.62 Hyp Configuration Register 2
The HCR2 characteristics are:
Purpose
Provides additional configuration controls for virtualization.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Configurations
HCR2 is architecturally mapped to AArch64 register HCR_EL2[63:32]. See B2.48 Hypervisor
Configuration Register, EL2 on page B2-433.
This register is accessible only at EL2 or EL3.
Attributes
HCR2 is a 32-bit register.
RES0
31 0
CD
ID
12
Figure B1-18 HCR2 bit assignments
[31:2]
Reserved, RES0.
ID, [1]
Stage 2 Instruction cache disable. When HCR.VM is 1, this forces all stage 2 translations for
instruction accesses to Normal memory to be Non-cacheable for the EL1/EL0 translation
regime. The possible values are:
0 No effect on the stage 2 of the EL1/EL0 translation regime for instruction accesses.
1 Forces all stage 2 translations for instruction accesses to Normal memory to be Non-
cacheable for the EL0/EL1 translation regime.
CD, [0]
Stage 2 Data cache disable. When HCR.VM is 1, this forces all stage 2 translations for data
accesses and translation table walks to Normal memory to be Non-cacheable for the EL1/EL0
translation regime. The possible values are:
0 No effect on the stage 2 of the EL1/EL0 translation regime for data accesses and translation
table walks.
1 Forces all stage 2 translations for data accesses and translation table walks to Normal
memory to be Non-cacheable for the EL0/EL1 translation regime.
B1 AArch32 system registers
B1.62 Hyp Configuration Register 2
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B1-246
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English