SWIO, [1]
Set/Way Invalidation Override. When 1, this causes EL1 execution of the data cache invalidate
by set/way instruction to be treated as data cache clean and invalidate by set/way. DCISW is
executed as DCCISW.
This bit is RES1.
VM, [0]
Second stage of Translation enable. When 1, this enables the second stage of translation for
execution in EL1 and EL0.
The reset value is 0.
To access the HCR:
MRC p15, 4, <Rt>, c1, c1, 0; Read Hyp Configuration Register
MCR p15, 4, <Rt>, c1, c1, 0; Write Hyp Configuration Register
Register access is encoded as follows:
Table B1-46 HCR access encoding
coproc opc1 CRn CRm opc2
1111 100 0001 0001 000
B1 AArch32 system registers
B1.61 Hyp Configuration Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-245
Non-Confidential
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