B2.51 AArch64 Debug Feature Register 0, EL1
The ID_AA64DFR0_EL1 characteristics are:
Purpose
Provides top level information of the debug system in the AArch64 Execution state.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_AA64DFR0_EL1 is architecturally mapped to external register EDDFR.
Attributes
ID_AA64DFR0_EL1 is a 64-bit register.
4 38 712 1116 1520 1924 2328 27
063
RES0 RES0 DebuggerTraceverPMUverBRPsWRPsCTX_CMPsRES0
32 31
Figure B2-25 ID_AA64DFR0_EL1 bit assignments
[63:32]
Reserved, RES0.
CTX_CMPs, [31:28]
Number of breakpoints that are context-aware, minus 1. These are the highest numbered
breakpoints:
0b0001 Two breakpoints are context-aware.
[27:24]
Reserved, RES0.
WRPs, [23:20]
The number of watchpoints minus 1:
0b0011 Four watchpoints.
[19:16]
Reserved, RES0.
BRPs, [15:12]
The number of breakpoints minus 1:
0b0101 Six breakpoints.
PMUver, [11:8]
Performance Monitors Extension version.
0b0001 Performance monitor system registers implemented, PMUv3.
Tracever, [7:4]
B2 AArch64 system registers
B2.51 AArch64 Debug Feature Register 0, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-444
Non-Confidential
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