A5.5 Invalidating or cleaning a cache
The processor automatically invalidates caches on reset unless suppressed with the
DBGL1RSTDISABLE or L2RSTDISABLE pins. It is therefore not necessary for software to
invalidate the caches on start-up.
DCIMVAC operations in AArch32 and DC IVAC instructions in AArch64 perform an invalidate of the
target address. If the data is dirty within the cluster then a clean is performed before the invalidate.
DCISW operations in AArch32 and DC ISW instructions in AArch64 perform both a clean and
invalidate of the target set/way. The values of HCR.SWIO and HCR_EL2.SWIO have no effect.
The Armv8-A architecture does not support an operation to invalidate the entire data cache. If this
function is required in software, it must be constructed by iterating over the cache geometry and
executing a series of individual invalidate by set/way instructions.
A5 Cache Behavior and Cache Protection
A5.5 Invalidating or cleaning a cache
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A5-82
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