ARM Cortex-A35 User Manual

A7.3 Support for memory types
The processor simplifies the coherency logic by downgrading some memory types.
• Memory that is marked as both Inner Write-Back Cacheable and Outer Write-Back Cacheable is
cached in the L1 data cache and the L2 cache.
• Memory that is marked Inner Write-Through is downgraded to Non-cacheable.
• Memory that is marked Outer Write-Through or Outer Non-cacheable is downgraded to Non-
cacheable, even if the inner attributes are Write-Back cacheable.
The attributes provided on ARCACHE or AWCACHE in AXI and ACE configurations or MemAttr and
SnpAttr in CHI configurations are these downgraded attributes and indicate how the interconnect must
treat the transaction.
A7 L2 Memory System
A7.3 Support for memory types
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English