Table C7-1 AArch64 debug register summary (continued)
Name Type Reset Width Description
DBGBCR4_EL1 RW - 32 C7.2 Debug Breakpoint Control Registers, EL1
on page C7-636
DBGBVR5_EL1 RW - 64 Debug Breakpoint Value Register 5
DBGBCR5_EL1 RW - 32 C7.2 Debug Breakpoint Control Registers, EL1
on page C7-636
OSECCR_EL1 RW - 32 Debug OS Lock Exception Catch Register
MDCCSR_EL0 RO - 32 Monitor Debug Comms Channel Status Register
DBGDTR_EL0 RW - 64 Debug Data Transfer Register, half-duplex
DBGDTRTX_EL0 WO - 32 Debug Data Transfer Register, Transmit, Internal View
DBGDTRRX_EL0 RO - 32 Debug Data Transfer Register, Receive, Internal View
DBGVCR32_EL2 RW - 32 Debug Vector Catch Register
MDRAR_EL1 RO Resets to the physical
address of the ROM
table +3.
64 Debug ROM Address Register
OSLAR_EL1 WO - 32 Debug OS Lock Access Register
OSLSR_EL1 RO
0x0000000A
32 Debug OS Lock Status Register
OSDLR_EL1 RW
0x00000000
32 Debug OS Double Lock Register
DBGPRCR_EL1 RW - 32 Debug Power/Reset Control Register
DBGCLAIMSET_EL1 RW
0x000000FF
32 Debug Claim Tag Set Register
DBGCLAIMCLR_EL1 RW
0x00000000
32 Debug Claim Tag Clear Register
DBGAUTHSTATUS_EL1 RO - 32 Debug Authentication Status Register
C7 AArch64 debug registers
C7.1 AArch64 debug register summary
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C7-635
Non-Confidential
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