ARM Cortex-A35 User Manual

C10.15 Performance Monitors Peripheral Identification Register 3
The PMPIDR3 characteristics are:
Purpose
Provides information to identify a Performance Monitor component.
Usage constraints
The PMPIDR3 can be accessed through the external debug interface.
The accessibility to the PMPIDR3 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
C2.2 External register access permissions to the PMU registers on page C2-587 describes the
condition codes.
Configurations
The PMPIDR3 is in the Debug power domain.
Attributes
See the register summary in C10.9 Memory-mapped PMU register summary on page C10-714.
RES0
31 0
34
CMOD
78
REVAND
Figure C10-11 PMPIDR3 bit assignments
[31:8]
Reserved, RES0.
REVAND, [7:4]
0x0 Part minor revision.
CMOD, [3:0]
0x0 Customer modified.
The PMPIDR3 can be accessed through the external debug interface, offset 0xFEC.
C10 PMU registers
C10.15 Performance Monitors Peripheral Identification Register 3
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C10-723
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English