A7.5 Handling of external aborts
The memory system handles external aborts using the synchronous abort mechanism, asynchronous
abort mechanism, or the nEXTERRIRQ pin as described in this section.
Synchronous abort mechanism
External aborts on the following accesses use the synchronous abort mechanism.
• All load accesses.
• All Store Exclusive accesses (STREX, STREXB, STREXH, STREXD, STXR, STXRB, STXRH,
STXP, STLXR, STLXRB, STLXRH, and STLXP).
Asynchronous abort mechanism
External aborts on the following accesses use the asynchronous abort mechanism.
• Stores to Device memory (except Store Exclusive accesses).
• Stores to Normal memory that is Inner Non-cacheable, Inner Write-Through, Outer Non-cacheable,
or Outer Write-Through (except Store Exclusive accesses).
• L1 data cache and L2 cache linefills that receive data from the interconnect in the dirty state.
nEXTERRIRQ pin
External aborts on the following accesses cause the nEXTERRIRQ pin to be asserted because the aborts
might not relate directly back to a specific core in the cluster.
• All store accesses to Normal memory that is both Inner write-back and Outer write-back.
• Evictions from the L1 data cache or L2 cache.
• DVM Complete transactions.
Related reference
B1.93 L2 Extended Control Register on page B1-305
A7 L2 Memory System
A7.5 Handling of external aborts
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