B2.46 Fault Address Register, EL3
The FAR_EL3 characteristics are:
Purpose
Holds the faulting Virtual Address for all synchronous instruction or data aborts, or exceptions
from a misaligned PC, taken to EL3.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
Configurations
There is no additional configuration data for FAR_EL3.
Attributes
FAR_EL3 is a 64-bit register.
VA
63 0
Figure B2-21 FAR_EL3 bit assignments
VA, [63:0]
The faulting Virtual Address for all synchronous instruction or data aborts, or an exception from
a misaligned PC, taken in EL3.
If a memory fault that sets the FAR is generated from one of the data cache instructions, this
field holds the address specified in the register argument of the instruction.
To access the FAR_EL3:
MRS <Xt>, FAR_EL3 ; Read EL3 Fault Address Register
MSR FAR_EL3, <Xt> ; Write EL3 Fault Address Register
Register access is encoded as follows:
Table B2-40 FAR_EL3 access encoding
op0 op1 CRn CRm op2
11 110 0110 0000 000
B2 AArch64 system registers
B2.46 Fault Address Register, EL3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-431
Non-Confidential
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