B2.2 AArch64 Identification registers
The following table shows the identification registers in AArch64 state.
Bits[63:32] are reset to 0x00000000 for all 64-bit registers in the table.
Table B2-1 AArch64 identification registers
Name Type Reset Width Description
MIDR_EL1 RO
0x411FD040
32 B2.83 Main ID Register, EL1 on page B2-510
MPIDR_EL1 RO - 64
B2.84 Multiprocessor Affinity Register, EL1 on page B2-512
The reset value depends on the primary inputs, CLUSTERIDAFF1 and
CLUSTERIDAFF2, and the number of cores that the device implements.
REVIDR_EL1 RO
0x00000000
32 B2.86 Revision ID Register, EL1 on page B2-518
ID_PFR0_EL1 RO
0x00000131
32 B2.67 AArch32 Processor Feature Register 0, EL1 on page B2-475
ID_PFR1_EL1 RO
0x10011011
32
B2.68 AArch32 Processor Feature Register 1, EL1 on page B2-477
Bits [31:28] are 0x1 if the GIC CPU interface is present and enabled, and
0x0 otherwise.
ID_DFR0_EL1 RO
0x03010066
32
B2.56 AArch32 Debug Feature Register 0, EL1 on page B2-453
Bits [19:16] are 0x1 if ETM is implemented, and 0x0 otherwise.
ID_AFR0_EL1 RO
0x00000000
32 B2.55 AArch32 Auxiliary Feature Register 0, EL1 on page B2-452
ID_MMFR0_EL1 RO
0x10201105
32 B2.63 AArch32 Memory Model Feature Register 0, EL1 on page B2-467
ID_MMFR1_EL1 RO
0x40000000
32 B2.64 AArch32 Memory Model Feature Register 1, EL1 on page B2-469
ID_MMFR2_EL1 RO
0x01260000
32 B2.65 AArch32 Memory Model Feature Register 2, EL1 on page B2-471
ID_MMFR3_EL1 RO
0x02102211
32 B2.66 AArch32 Memory Model Feature Register 3, EL1 on page B2-473
ID_ISAR0_EL1 RO
0x02101110
32 B2.57 AArch32 Instruction Set Attribute Register 0, EL1 on page B2-455
ID_ISAR1_EL1 RO
0x13112111
32 B2.58 AArch32 Instruction Set Attribute Register 1, EL1 on page B2-457
ID_ISAR2_EL1 RO
0x21232042
32 B2.59 AArch32 Instruction Set Attribute Register 2, EL1 on page B2-459
ID_ISAR3_EL1 RO
0x01112131
32 B2.60 AArch32 Instruction Set Attribute Register 3, EL1 on page B2-461
ID_ISAR4_EL1 RO
0x00011142
32 B2.61 AArch32 Instruction Set Attribute Register 4, EL1 on page B2-463
ID_ISAR5_EL1 RO
0x00011121
32
B2.62 AArch32 Instruction Set Attribute Register 5, EL1 on page B2-465
ID_ISAR5_EL1 has the value 0x00010001 if the Cryptographic Extension
is not implemented and enabled.
ID_AA64PFR0_EL1 RO
0x01002222
64
B2.54 AArch64 Processor Feature Register 0, EL1 on page B2-450
Bits [27:24] are 0x1 if the GIC CPU interface is present and enabled, and
0x0 otherwise.
Bits [23:16] are 0x00 if the Advanced SIMD and floating-point support is
implemented, and 0xFF otherwise.
ID_AA64PFR1_EL1 RO
0x00000000
64
AArch64 Processor Feature Register 1
ID_AA64DFR0_EL1 RO
0x10305106
64 B2.51 AArch64 Debug Feature Register 0, EL1 on page B2-444
B2 AArch64 system registers
B2.2 AArch64 Identification registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
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