A6.4 About the internal exclusive monitor
The internal exclusive monitor is a state machine that manages Load-Exclusive or Store-Exclusive
instructions, and Clear-Exclusive (CLREX) instructions. Its two states are open and exclusive.
You can use the Load-Exclusive or Store-Exclusive accesses and the Clear-Exclusive instructions to
construct semaphores to ensure synchronization between different processes running on the core and also
between different cores that are using the same coherent memory locations for the semaphore.
A Load-Exclusive instruction tags a small block of memory for exclusive access. The size of the tagged
block is defined by CTR.ERG as 16 words, one cache line.
A Load-exclusive/Store-exclusive instruction is any one of the following:
• In the A64 instruction set, any instruction that has a mnemonic starting with LDX, LDAX, STX, or STLX.
• In the A32 and T32 instruction sets, any instruction that has a mnemonic starting with LDREX, STREX,
LDAEX, or STLEX.
A Load-Exclusive instruction that causes a transaction with ARLOCKM for AXI/ACE, or Excl for CHI,
set to HIGH is expected to receive an EXOKAY response. An OKAY response to a transaction with
ARLOCKM for AXI/ACE, or Excl for CHI, set to HIGH indicates that exclusive accesses are not
supported at the address of the transaction and causes a Data Abort exception to be taken with a Data
Fault Status Code of:
• 0b110101, when using the long descriptor format.
• 0b10101, when using the short descriptor format.
A Load-Exclusive instruction causes ARLOCKM for AXI to be set to HIGH if the memory attributes
are:
• Device.
• Normal Inner Non-cacheable and Outer Non-cacheable.
• Normal Inner is not Write-Back or Outer is not Write-Back, and Inner Shareable.
• Normal Inner is not Write-Back or Outer is not Write-Back, and Outer Shareable.
A Load-Exclusive instruction causes ARLOCKM for ACE or Excl for CHI, to be set to HIGH if the
memory attributes are:
• Device.
• Normal Inner Non-cacheable and Outer Non-cacheable.
• Normal Inner Write-Back, Outer Write-Back, Outer Shareable, and BROADCASTOUTER is set to
HIGH.
• Normal Inner Write-Back, Outer Write-Back, Inner Shareable, and BROADCASTINNER is set to
HIGH.
• Normal Inner is not Write-Back or Outer is not Write-Back, and Inner Shareable.
• Normal Inner is not Write-Back or Outer is not Write-Back, and Outer Shareable.
In cases where there is an intervening store operation between an exclusive load and an exclusive store
from the same core, the intermediate store does not produce any direct effect on the internal exclusive
monitor. The local monitor is in the Exclusive Access state after the exclusive load, remains in the
Exclusive Access state after the store, and returns to the Open Access state only after the exclusive store,
a CLREX instruction, or an exception return.
However, if the exclusive code sequence is accessing an address in cacheable memory, any cache line
eviction that contains that address clears the monitor. Arm therefore recommends that no load or store
instructions are placed between the exclusive load and the exclusive store because these additional
instructions can cause a cache eviction. Any data cache maintenance instruction can also clear the
exclusive monitor.
Related reference
A8.3 AXI transactions on page A8-108
A9.4 ACE transactions on page A9-117
A6 L1 Memory System
A6.4 About the internal exclusive monitor
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A6-93
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