C1.7 Debug signals
The DBGPWRDUP and DBGL1RSTDISABLE signals are subject to particular rules.
You must set the DBGPWRDUP signal LOW before removing power to the processor domain. After
power is restored to the processor domain, the DBGPWRDUP signal must be asserted HIGH. The
EDPRSR.PU bit reflects the value of this DBGPWRDUP signal. DBGPWRDUP must be tied HIGH if
the particular implementation does not support separate processor and SCU power domains.
When you set it HIGH, the DBGL1RSTDISABLE input signal disables the automatic, hardware-
controlled invalidation with nCORERESET or nCPUPORESET of the L1 data cache after the
processor is reset. You must use DBGL1RSTDISABLE only to debug a reset that an external watchdog
triggered. This signal makes the contents of the L1 data cache from before the reset observable after the
reset. If reset is asserted while an L1 data cache eviction or L1 data cache fetch is performed, the
accuracy of those cache entries is not guaranteed. You must not use the DBGL1RSTDISABLE signal to
disable the automatic, hardware controlled invalidation of the L1 data cache in normal processor
powerup sequences. This is because there is no guarantee that the L1 data cache invalidation sequence is
synchronized to the duplicate L1 tags in the SCU. The DBGL1RSTDISABLE signal applies to all cores
in the cluster. Each core samples the signal when nCORERESET or nCPUPORESET is asserted. If the
functionality offered by the DBGL1RSTDISABLE input signal is not required, the input must be tied to
LOW.
Related information
A.14 Debug signals on page Appx-A-871
C1 Debug
C1.7 Debug signals
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C1-583
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