B1.69 Hyp System Trap Register
The HSTR characteristics are:
Purpose
Controls trapping to Hyp mode of Non-secure accesses, at EL1 or lower, of use of T32EE, or the
CP15 primary registers, {c0-c3,c5-c13,c15}.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW -
Configurations
HSTR is architecturally mapped to AArch64 register HSTR_EL2. See B2.50 Hyp System Trap
Register, EL2 on page B2-441.
This register is accessible only at EL2 or EL3.
Attributes
HSTR is a 32-bit register.
31 0
RES0
1234567891011121314151617
TTEE
RES0
T15
T13
T12
T11
T10
T9
T8
T0
T1
T2
T3
RES0
T5
T6
T7
Figure B1-25 HSTR bit assignments
[31:17]
Reserved, RES0.
TTEE, [16]
Trap T32EE. This value is:
0 T32EE is not supported.
T15, [15]
Trap coprocessor primary register CRn = 15. The possible values are:
0 Has no effect on Non-secure accesses to CP15 registers.
1 Trap valid Non-secure accesses to coprocessor primary register CRn = 15 to Hyp
mode.
The reset value is 0.
B1 AArch32 system registers
B1.69 Hyp System Trap Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-259
Non-Confidential
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