ARM Cortex-A35 User Manual

C6.5 Debug Device ID Register
The DBGDEVID characteristics are:
Purpose
Specifies the version of the Debug architecture is implemented, and some features of the debug
implementation.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Configurations
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
See C6.1 AArch32 debug register summary on page C6-620.
CIDMask
31 4 3 0
PCsample
28 27 24 23 20 19 16 15 12 11 8 7
AuxRegs DoubleLock VirtExtns
VectorCatch
BPAddrMask
WPAddrMask
Figure C6-4 DBGDEVID bit assignments
CIDMask, [31:28]
Specifies the level of support for the Context ID matching breakpoint masking capability. This
value is:
0x0 Context ID masking is not implemented.
AuxRegs, [27:24]
Specifies support for the Debug External Auxiliary Control Register. This value is:
0x0 None supported.
DoubleLock, [23:20]
Specifies support for the Debug OS Double Lock Register. This value is:
0x1 The processor supports Debug OS Double Lock Register.
VirtExtns, [19:16]
Specifies whether EL2 is implemented. This value is:
0x1 The processor implements EL2.
VectorCatch, [15:12]
Defines the form of the vector catch event implemented. This value is:
0x0 The processor implements address matching form of vector catch.
BPAddrMask, [11:8]
C6 AArch32 debug registers
C6.5 Debug Device ID Register
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English