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ARM Cortex-A35 User Manual

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C12.8 CTI Peripheral Identification Register 2
The CTIPIDR2 characteristics are:
Purpose
Provides information to identify a CTI component.
Usage constraints
The accessibility of CTIPIDR2 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
C12.2 External register access permissions to the CTI registers on page C12-828 describes the
condition codes.
Configurations
CTIPIDR2 is in the Debug power domain.
CTIPIDR2 is optional to implement in the external register interface.
Attributes
See the register summary in C12.1 Cross trigger register summary on page C12-826.
RES0
31 0
34
DES_1
78
Revision
JEDEC
2
Figure C12-5 CTIPIDR2 bit assignments
[31:8]
Reserved, RES0.
Revision, [7:4]
0x3 r1p0.
JEDEC, [3]
0b1 RES1. Indicates a JEP106 identity code is used.
DES_1, [2:0]
0b011 Arm Limited. This is the most significant nibble of JEP106 ID code.
CTIPIDR2 can be accessed through the external debug interface, offset 0xFE8.
C12 CTI registers
C12.8 CTI Peripheral Identification Register 2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C12-835
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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