C10.16 Performance Monitors Peripheral Identification Register 4
The PMPIDR4 characteristics are:
Purpose
Provides information to identify a Performance Monitor component.
Usage constraints
The PMPIDR4 can be accessed through the external debug interface.
The accessibility to the PMPIDR4 by condition code is:
Off DLK OSLK EPMAD SLK Default
- - - - RO RO
C2.2 External register access permissions to the PMU registers on page C2-587 describes the
condition codes.
Configurations
The PMPIDR4 is in the Debug power domain.
Attributes
See the register summary in C10.9 Memory-mapped PMU register summary on page C10-714.
RES0
31 0
34
DES_2
78
Size
Figure C10-12 PMPIDR4 bit assignments
[31:8]
Reserved, RES0.
Size, [7:4]
0x0 Size of the component. Log2 the number of 4KB pages from the start of the
component to the end of the component ID registers.
DES_2, [3:0]
0x4 Arm Limited. This is the least significant nibble JEP106 continuation code.
The PMPIDR4 can be accessed through the external debug interface, offset 0xFD0.
C10 PMU registers
C10.16 Performance Monitors Peripheral Identification Register 4
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
C10-724
Non-Confidential
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