ARM Cortex-A35 User Manual

B1.50 DFSR with Short-descriptor translation table format
DFSR has a specific format when using the Short-descriptor translation table format.
The following figure shows the DFSR bit assignments when using the Short-descriptor translation table
format.
31 14 13 12 11 10 9 8 7 4 3 0
RES0 0
CM
ExT
WnR
FS[4]
RES0
Domain FS[3:0]
Figure B1-13 DFSR bit assignments for Short-descriptor translation table format
[31:14]
Reserved, RES0.
CM, [13]
Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance
operation generated the fault:
0 Abort not caused by a cache maintenance operation.
1 Abort caused by a cache maintenance operation.
ExT, [12]
External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:
0 External abort marked as DECERR.
1 External abort marked as SLVERR.
For aborts other than external aborts this bit always returns 0.
WnR, [11]
Write not Read bit. This field indicates whether the abort was caused by a write or a read access:
0 Abort caused by a read access.
1 Abort caused by a write access.
For faults on CP15 cache maintenance operations, including the VA to PA translation
operations, this bit always returns a value of 1.
FS[4], [10]
Part of the Fault Status field. See bits [3:0] in this table.
[9]
RAZ.
[8]
Reserved, RES0.
Domain, [7:4]
Specifies which of the 16 domains, D15-D0, was being accessed when a data fault occurred.
For permission faults that generate Data Abort exception, this field is UNKNOWN. Armv8
deprecates any use of the domain field in the DFSR.
B1 AArch32 system registers
B1.50 DFSR with Short-descriptor translation table format
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English