ARM Cortex-A35 User Manual

B1.112 TTBCR with Long-descriptor translation table format
TTBCR has a specific format when using the Long-descriptor translation table format. TTBCR.EAE
determines which format of the register is in use.
The following figure shows the TTBCR bit assignments when TTBCR.EAE is 1.
31 30 29 28 27 26 25 24 23 22 21 19 18 16 15 14 13 12 11 10 9 8 7 6 3 2
SH1 A1 T1SZ SH0 RES0 T0SZ
EAE
EPD0
0
RES0
ORGN1
IRGN1
EPD1
IRGN0
ORGN0
RES0 RES0
Figure B1-62 TTBCR bit assignments, TTBCR.EAE is 1
EAE, [31]
Extended Address Enable:
1 Use the 40-bit translation system, with the Long-descriptor translation table
format.
[30]
Reserved, RES0.
SH1, [29:28]
Shareability attribute for memory associated with translation table walks using TTBR1:
0b00 Non-shareable.
0b10 Outer Shareable.
0b11 Inner Shareable.
Other values are reserved.
Resets to 0.
ORGN1, [27:26]
Outer cacheability attribute for memory associated with translation table walks using TTBR1:
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
Resets to 0.
IRGN1, [25:24]
Inner cacheability attribute for memory associated with translation table walks using TTBR1:
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
Resets to 0.
EPD1, [23]
B1 AArch32 system registers
B1.112 TTBCR with Long-descriptor translation table format
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English