ARM Cortex-A35 User Manual

B2.62 AArch32 Instruction Set Attribute Register 5, EL1
The ID_ISAR5_EL1 characteristics are:
Purpose
Provides information about the instruction sets that the processor implements.
The optional Advanced SIMD and floating-point support is not included in the base product of
the processor. Arm requires licensees to have contractual rights to obtain the Advanced SIMD
and floating-point support.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Configurations
ID_ISAR5_EL1 is architecturally mapped to AArch32 register ID_ISAR5. See
B1.79 Instruction Set Attribute Register 5 on page B1-279.
Attributes
ID_ISAR5_EL1 is a 32-bit register.
31
12 11 8 7 0
RES0 SHA1 AES SEVLSHA2
4 316 1520 19
CRC32
Figure B2-35 ID_ISAR5_EL1 bit assignments
[31:20]
Reserved, RES0.
CRC32, [19:16]
Indicates whether CRC32 instructions are implemented in AArch32 state:
0x1 CRC32 instructions are implemented.
SHA2, [15:12]
Indicates whether SHA2 instructions are implemented in AArch32 state:
0x0 Cryptographic Extensions are not implemented or are disabled.
0x1 SHA256H, SHA256H2, SHA256SU0, and SHA256SU1 instructions are implemented.
SHA1, [11:8]
Indicates whether SHA1 instructions are implemented in AArch32 state:
0x0 Cryptographic Extensions are not implemented or are disabled.
0x1 SHA1C, SHA1P, SHA1M, SHA1H, SHA1SU0, and SHA1SU1 instructions are implemented.
AES, [7:4]
Indicates whether AES instructions are implemented in AArch32 state:
0x0 Cryptographic Extensions are not implemented or are disabled.
B2 AArch64 system registers
B2.62 AArch32 Instruction Set Attribute Register 5, EL1
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B2-465
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English