B1.116 Translation Table Base Register 1
The TTBR1 characteristics are:
Purpose
Holds the base address of translation table 1, and information about the memory it occupies.
This is one of the translation tables for the stage 1 translation of memory accesses from modes
other than Hyp mode.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
Used in conjunction with the TTBCR. When the 64-bit TTBR1 format is used, cacheability and
shareability information is held in the TTBCR and not in TTBR1. See B1.110 Translation Table
Base Control Register on page B1-341.
Configurations
TTBR1 (NS) is architecturally mapped to AArch64 register TTBR0_EL1. See
B2.98 Translation Table Base Register 1, EL1 on page B2-548.
If EL3 is using AArch32, there are separate Secure and Non-secure instances of this register.
If EL3 is using AArch32, write access to TTBR1(S) is disabled when the CP15SDISABLE2
signal is asserted HIGH.
Attributes
TTBR1 is:
• A 32-bit register when TTBCR.EAE is 0.
• A 64-bit register when TTBCR.EAE is 1.
There are two formats for this register. TTBCR.EAE determines which format of the register is used.
B1 AArch32 system registers
B1.116 Translation Table Base Register 1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-350
Non-Confidential
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