ARM Cortex-A35 User Manual

B2.21 Auxiliary Control Register, EL3
The ACTLR_EL3 characteristics are:
Purpose
Controls write access to IMPLEMENTATION DEFINED registers in EL2, such as CPUACTLR,
CPUECTLR, L2CTLR, L2ECTLR, and L2ACTLR.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - - RW RW
Configurations
ACTLR_EL3 is mapped to AArch32 register ACTLR (S). See B1.32 Auxiliary Control Register
on page B1-193.
Attributes
ACTLR_EL3 is a 32-bit register.
RES0
31 7 6 5 1 0
RES0
4 3 2
L2ACTLR_EL1 access control
L2ECTLR_EL1 access control
L2CTLR_EL1 access control
CPUECTLR_EL1 access control
CPUACTLR_EL1 access control
Figure B2-2 ACTLR_EL3 bit assignments
[31:7]
Reserved, RES0.
L2ACTLR_EL1 access control, [6]
L2ACTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
1 The register is write accessible from EL2.
L2ECTLR_EL1 access control, [5]
L2ECTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
1 The register is write accessible from EL2.
L2CTLR_EL1 access control, [4]
L2CTLR_EL1 write access control. The possible values are:
0 The register is not write accessible from a lower exception level. This is the reset value.
1 The register is write accessible from EL2.
[3:2]
Reserved, RES0.
B2 AArch64 system registers
B2.21 Auxiliary Control Register, EL3
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English