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ARM Cortex-A35 User Manual

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B2.1 AArch64 register summary
This section gives a summary of the system registers in the AArch64 Execution state.
For more information on using the system registers, see the Arm
®
Architecture Reference Manual Armv8,
for Armv8-A architecture profile.
The following subsections describe the system registers by functional group:
B2.2 AArch64 Identification registers on page B2-363.
B2.3 AArch64 Exception handling registers on page B2-365.
B2.4 AArch64 Virtual memory control registers on page B2-366.
B2.5 AArch64 Other System control registers on page B2-368.
B2.6 AArch64 Cache maintenance operations on page B2-369.
B2.7 AArch64 TLB maintenance operations on page B2-370.
B2.8 AArch64 Address translation operations on page B2-371.
B2.9 AArch64 Miscellaneous operations on page B2-372.
B2.10 AArch64 Performance monitor registers on page B2-373.
B2.11 AArch64 Reset registers on page B2-375.
B2.12 AArch64 Secure registers on page B2-376.
B2.13 AArch64 Virtualization registers on page B2-377.
B2.14 AArch64 EL2 TLB maintenance operations on page B2-379.
B2.15 AArch64 GIC system registers on page B2-380.
B2.16 AArch64 Generic Timer registers on page B2-382.
B2.17 AArch64 Thread registers on page B2-383.
B2.18 AArch64 Implementation defined registers on page B2-384.
B2 AArch64 system registers
B2.1 AArch64 register summary
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-362
Non-Confidential

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ARM Cortex-A35 Specifications

General IconGeneral
BrandARM
ModelCortex-A35
CategoryComputer Hardware
LanguageEnglish

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