B2.73 L2 Auxiliary Control Register, EL1
The L2ACTLR_EL1 characteristics are:
Purpose
Provides configuration and control options for the L2 memory system.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
The L2ACTLR_EL1:
• This register can be written only when the L2 memory system is idle. Arm recommends that
you write to this register after a powerup reset before the MMU is enabled and before any
ACE, CHI or ACP traffic has begun.
If the register must be modified after a powerup reset sequence, to idle the L2 memory
system, you must take the following steps:
1. Disable the MMU from each core followed by an ISB to ensure the MMU disable
operation is complete, then followed by a DSB to drain previous memory transactions.
2. Ensure that the system has no outstanding AC channel coherence requests to the
Cortex‑A35 processor.
3. Ensure that the system has no outstanding ACP requests to the Cortex‑A35 processor.
When the L2 memory system is idle, the processor can update the L2ACTLR_EL1 followed by
an ISB. After the L2ACTLR_EL1 is updated, the MMUs can be enabled and normal ACE and
ACP traffic can resume.
Configurations
There is one copy of this register that is used in both Secure and Non-secure states.
L2ACTLR_EL1 is mapped to the AArch32 L2ACTLR register. See B1.91 L2 Auxiliary Control
Register on page B1-301.
Attributes
L2ACTLR_EL1 is a 32-bit register.
31
30 29 15 14 13 4 3 2
0
RES0RES0
Disable clean/evict push to external
Enable UniqueClean evictions with data
L2 Victim Control
RES0
L2DEIEN
28 25 24
RES0
L2TEIEN
Figure B2-45 L2ACTLR_EL1 bit assignments
[31:30]
L2 Victim Control.
0b10 This is the default value. Software must not change it.
L2DEIEN, [29]
B2 AArch64 system registers
B2.73 L2 Auxiliary Control Register, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-486
Non-Confidential
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