C9.4 ROM entry registers
The characteristics of the ROMENTRYn are:
Purpose
Indicates to a debugger whether the debug component is present in the debug logic of the
processor. There are 16 ROMENTRY registers in the Cortex‑A35 processor.
Usage constraints
These registers are accessible as follows:
Off DLK OSLK EDAD SLK Default
- - - - - RO
C1.4 External access permissions to debug registers on page C1-579 describes the condition
codes.
Configurations
Attributes
See C9.3 ROM table register summary on page C9-672.
31
0
RES0
Format
1211
Component present
Address offset
12
Figure C9-1 ROMENTRY bit assignments
Address offset, [31:12]There is one copy of this register that is used in both Secure and Non-secure
states.
Address offset for the debug component.
There is one copy of this register that is used in both Secure andNegative values of address
offsets are permitted using the two’s complement of the offset.
[11:2]
Reserved, RES0.
Format, [1]
Format of the ROM table entry. The value for all ROMENTRY registers is:
0 End marker.
1 32-bit format.
Component present, [0]
Indicates whether the component is present:
0 Component is not present.
1 Component is present.
The debug, CTI, and PMU components for core 0 are always present.
The Physical Address of a debug component is determined by shifting the address offset 12 places to the
left and adding the result to the Physical Address of the Cortex‑A35 processor ROM table.
C9 ROM table
C9.4 ROM entry registers
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