ARM Cortex-A35 User Manual

B2.52 AArch64 Instruction Set Attribute Register 0, EL1
The ID_AA64ISAR0_EL1 characteristics are:
Purpose
Provides information about the optional cryptographic instructions that the processor can
support.
The optional Cryptographic engine is not included in the base product of the processor. Arm
requires licensees to have contractual rights to obtain the Cortex‑A35 Cryptographic engine.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RO RO RO RO RO
Attributes
ID_AA64ISAR0_EL1 is a 64-bit register.
63 0
RES0 RES0AESSHA1SHA2
16 15 12 11 8 7 4 3
CRC32
20 19
Figure B2-26 ID_AA64ISAR0_EL1 bit assignments
[63:20]
Reserved, RES0.
CRC32, [19:16]
Indicates whether CRC32 instructions are implemented.
0x1 CRC32 instructions are implemented.
SHA2, [15:12]
Indicates whether SHA2 instructions are implemented. The possible values are:
0b0000 No SHA2 instructions implemented. This is the value if the implementation does not
include the Cryptographic Extension, or if it is disabled.
0b0001 SHA256H, SHA256H2, SHA256U0, and SHA256U1 implemented. This is the value if the
implementation includes the Cryptographic Extension.
All other values reserved.
SHA1, [11:8]
Indicates whether SHA1 instructions are implemented. The possible values are:
0b0000 No SHA1 instructions implemented. This is the value if the implementation does not
include the Cryptographic Extension.
0b0001 SHA1C, SHA1P, SHA1M, SHA1SU0, and SHA1SU1 implemented. This is the value if the
implementation includes the Cryptographic Extension.
All other values reserved.
AES, [7:4]
B2 AArch64 system registers
B2.52 AArch64 Instruction Set Attribute Register 0, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-446
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English