ARM Cortex-A35 User Manual

A4.17 Q-channel
Q-channel enables:
• The controller to manage entry to, and exit from, a device quiescent state. Quiescence management is
typically of, but not restricted to, clock gated, and power gated retention states, of the device or
device partitions.
• The capability to indicate a requirement for exit from the quiescent state. The associated signaling
can contain contributions from other devices in the same power domain.
• Optional device capability to deny a quiescence request.
• Safe asynchronous interfacing across clock domains.
For more information, see the Low Power Interface Specification: Arm Q-Channel and P-Channel
Interfaces.
A4 Power Management
A4.17 Q-channel
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A4-76
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English