ARM Cortex-A35

A4.17 Q-channel
Q-channel enables:
• The controller to manage entry to, and exit from, a device quiescent state. Quiescence management is
typically of, but not restricted to, clock gated, and power gated retention states, of the device or
device partitions.
• The capability to indicate a requirement for exit from the quiescent state. The associated signaling
can contain contributions from other devices in the same power domain.
• Optional device capability to deny a quiescence request.
• Safe asynchronous interfacing across clock domains.
For more information, see the Low Power Interface Specification: Arm Q-Channel and P-Channel
Interfaces.
A4 Power Management
A4.17 Q-channel
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A4-76
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