A9.3 ACE privilege information
ACE provides information about the privilege level of an access on the ARPROTM[0] and
AWPROTM[0] signals. However, when accesses might be cached or merged together, the resulting
transaction can have both privileged and unprivileged data combined. If this happens, the processor
marks the transaction as privileged, even if it was initiated by an unprivileged process.
The following table shows exception levels and corresponding ARPROTM[0] and AWPROTM[0]
values.
Table A9-3 ARPROT and AWPROT values
Processor exception level Type of access
Value of ARPROT[0] and
AWPROT[0]
EL0, EL1, EL2, EL3 Cacheable read access Privileged access
EL0 Device, or normal Non-cacheable read access Unprivileged access
EL1, EL2, EL3 Privileged access
EL0, EL1, EL2, EL3 Cacheable write access Privileged access
EL0 Device, nGnRnE, nGnRE, and nGRE write Unprivileged access
EL1, EL2, EL3 Privileged access
EL0 Normal Non-cacheable or Device GRE write, except for STREX,
STREXB, STREXH, STREXD, STXR, STXRB, STXRH, STXP, STLXR,
STLXRB, STLXRH, and STLXP to shareable memory
Privileged access
EL0 Normal Non-cacheable write for STREX, STREXB, STREXH,
STREXD, STXR STXRB, STXRH, STXP, STLXR, STLXRB, STLXRH,
and STLXP to shareable memory
Unprivileged access
EL1, EL2, EL3 Normal Non-cacheable write Privileged access
EL0, EL1, EL2, EL3 TLB pagewalk Privileged access
A9 ACE Master Interface
A9.3 ACE privilege information
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
A9-116
Non-Confidential
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