ARM Cortex-A35 User Manual

B2.35 Cache Type Register, EL0
The CTR_EL0 characteristics are:
Purpose
Provides information about the architecture of the caches.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
Config RO RO RO RO RO
This register is accessible at EL0 when SCTLR_EL1.UCT is set to 1.
Configurations
CTR_EL0 is architecturally mapped to AArch32 register CTR. See B1.46 Cache Type Register
on page B1-219.
Attributes
CTR_EL0 is a 32-bit register.
IminLine
31 30 28 27 24 23 20 19 16 15 14 13 4 3 0
RES0 CWG ERG DminLine L1Ip RES0
RES1
Figure B2-10 CTR_EL0 bit assignments
[31]
Reserved, RES1.
[30:28]
Reserved, RES0.
CWG, [27:24]
Cache Write-Back granule. Log
2
of the number of words of the maximum size of memory that
can be overwritten as a result of the eviction of a cache entry that has had a memory location in
it modified:
0x4 Cache Write-Back granule size is 16 words.
ERG, [23:20]
Exclusives Reservation Granule. Log
2
of the number of words of the maximum size of the
reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive
instructions:
0x4 Exclusive reservation granule size is 16 words.
DminLine, [19:16]
Log
2
of the number of words in the smallest cache line of all the data and unified caches that the
processor controls:
0x4 Smallest data cache line size is 16 words.
L1lp, [15:14]
B2 AArch64 system registers
B2.35 Cache Type Register, EL0
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B2-410
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English