ARM Cortex-A35 User Manual

L1 Instruction cache policy. Indicates the indexing and tagging policy for the L1 Instruction
cache:
0b10 Virtually Indexed Physically Tagged (VIPT).
[13:4]
Reserved, RES0.
IminLine, [3:0]
Log
2
of the number of words in the smallest cache line of all the instruction caches that the
processor controls.
0x4 Smallest instruction cache line size is 16 words.
To access the CTR_EL0:
MRS <Xt>, CTR_EL0 ; Read CTR_EL0 into Xt
Register access is encoded as follows:
Table B2-26 CTR_EL0 access encoding
op0 op1 CRn CRm op2
11 011 0000 0000 001
B2 AArch64 system registers
B2.35 Cache Type Register, EL0
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-411
Non-Confidential

ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English