B2.97 Translation Table Base Register 0, EL1
The TTBR0_EL1 characteristics are:
Purpose
Holds the base address of translation table 0, and information about the memory it occupies.
This is one of the translation tables for the stage 1 translation of memory accesses from modes
other than Hyp mode.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- RW RW RW RW RW
Any of the fields in this register are permitted to be cached in a TLB.
Configurations
TTBR0_EL1 is architecturally mapped to AArch32 register TTBR0. See B1.113 Translation
Table Base Register 0 on page B1-346.
Attributes
TTBR0_EL1 is 64-bit register.
BADDR[47:x]
ASID
4748 063
Figure B2-68 TTBR0_EL1 bit assignments
ASID, [63:48]
An ASID for the translation table base address. The TCR_EL1.A1 field selects either
TTBR0_EL1.ASID or TTBR1_EL1.ASID.
BADDR[47:x], [47:0]
Translation table base address, bits[47:x]. Bits [x-1:0] are RES0.
x is based on the value of TCR_EL1.T0SZ, the stage of translation, and the memory translation
granule size.
For instructions on how to calculate it, see the Arm
®
Architecture Reference Manual Armv8, for
Armv8-A architecture profile
The value of x determines the required alignment of the translation table, that must be aligned to
2
x
bytes.
If bits [x-1:0] are not all zero, this is a misaligned Translation Table Base Address. Its effects are
CONSTRAINED UNPREDICTABLE, where bits [x-1:0] are treated as if all the bits are zero. The value
read back from those bits is the value written.
To access the TTBR0_EL1:
MRS <Xt>, TTBR0_EL1 ; Read TTBR0_EL1 into Xt
MSR TTBR0_EL1, <Xt> ; Write Xt to TTBR0_EL1
Register access is encoded as follows:
B2 AArch64 system registers
B2.97 Translation Table Base Register 0, EL1
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-546
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