B2.105 Virtualization Translation Control Register, EL2
The VTCR_EL2 characteristics are:
Purpose
Controls the translation table walks required for the stage 2 translation of memory accesses from
Non-secure EL0 and EL1, and holds cacheability and shareability information for the accesses.
Usage constraints
This register is accessible as follows:
EL0 EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Any of the bits in VTCR_EL2 are permitted to be cached in a TLB.
Configurations
VTCR_EL2 is architecturally mapped to AArch32 register VTCR. See B1.122 Virtualization
Translation Control Register on page B1-357.
Attributes
VTCR_EL2 is a 32-bit register.
31
0
RES0
567891011121314151617
TG0
ORGN0
IRGN0
1819
PS SH0 SL0 T0SZ
30
RES1
Figure B2-76 VTCR_EL2 bit assignments
[31]
Reserved, RES1.
[30:19]
Reserved, RES0.
PS, [18:16]
Physical Address Size. The possible values are:
0b000 32 bits, 4GB.
0b001 36 bits, 64GB.
0b010 40 bits, 1TB.
All other values are reserved.
TG0, [15:14]
Granule size for the corresponding VTTBR_EL2.
0b00 4KB.
0b10 16KB.
0b01 64KB.
0b11 Reserved.
All other values are not supported.
B2 AArch64 system registers
B2.105 Virtualization Translation Control Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-556
Non-Confidential
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