SH0, [13:12]
Shareability attribute for memory associated with translation table walks using VTTBR_EL2.
0b00 Non-shareable.
0b01 Reserved.
0b10 Outer Shareable.
0b11 Inner Shareable.
ORGN0, [11:10]
Outer cacheability attribute for memory associated with translation table walks using
VTTBR_EL2.
0b00 Normal memory, Outer Non-cacheable.
0b01 Normal memory, Outer Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Outer Write-Through Cacheable.
0b11 Normal memory, Outer Write-Back no Write-Allocate Cacheable.
IRGN0, [9:8]
Inner cacheability attribute for memory associated with translation table walks using
VTTBR_EL2.
0b00 Normal memory, Inner Non-cacheable.
0b01 Normal memory, Inner Write-Back Write-Allocate Cacheable.
0b10 Normal memory, Inner Write-Through Cacheable.
0b11 Normal memory, Inner Write-Back no Write-Allocate Cacheable.
SL0, [7:6]
Starting level of the VTCR_EL2 addressed region.
T0SZ, [5:0]
The size offset of the memory region addressed by VTTBR_EL2. The region size is 2
(64-T0SZ)
bytes.
To access the VTCR_EL2:
MRS <Xt>, VTCR_EL2 ; Read VTCR_EL2 into Xt
MSR VTCR_EL2, <Xt> ; Write Xt to VTCR_EL2
Register access is encoded as follows:
Table B2-98 VTCR_EL2 access encoding
op0 op1 CRn CRm op2
11 100 0010 0001 010
B2 AArch64 system registers
B2.105 Virtualization Translation Control Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-557
Non-Confidential
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