ARM Cortex-A35 User Manual

Chapter A5
Cache Behavior and Cache Protection
This chapter describes the CPU and SCU cache protection features of the Cortex‑A35 processor.
It contains the following sections:
• A5.1 Cached memory types on page A5-78.
• A5.2 Coherency between data caches with the MOESI protocol on page A5-79.
• A5.3 Cache misses, unexpected cache hits, and speculative fetches on page A5-80.
• A5.4 Disabling a cache on page A5-81.
• A5.5 Invalidating or cleaning a cache on page A5-82.
• A5.6 About read allocate mode on page A5-83.
• A5.7 About cache protection on page A5-84.
• A5.8 Error reporting on page A5-86.
• A5.9 Error injection on page A5-87.
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English