B1.83 Memory Model Feature Register 3
The ID_MMFR3 characteristics are:
Purpose
Provides information about the memory model and memory management support in AArch32.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_MMFR0, ID_MMFR1, and ID_MMFR2. See:
• B1.80 Memory Model Feature Register 0 on page B1-281
• B1.81 Memory Model Feature Register 1 on page B1-283
• B1.82 Memory Model Feature Register 2 on page B1-285
Configurations
ID_MMFR3 is architecturally mapped to AArch64 register ID_MMFR3_EL1. See
B2.66 AArch32 Memory Model Feature Register 3, EL1 on page B2-473.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_MMFR3 is a 32-bit register.
31
12 11 8 7 04 328 27 24 23 20 19 16 15
ReservedCohWalkCMemSzSupersec MaintBcst BPMaint CMaintSW CMaintVA
Figure B1-38 ID_MMFR3 bit assignments
Supersec, [31:28]
Supersections. Indicates support for supersections:
0x0 Supersections supported.
CMemSz, [27:24]
Cached Memory Size. Indicates the size of physical memory supported by the processor caches:
0x2 1TByte, corresponding to a 40-bit physical address range.
CohWalk, [23:20]
Coherent walk. Indicates whether translation table updates require a clean to the point of
unification:
0x1 Updates to the translation tables do not require a clean to the point of unification to
ensure visibility by subsequent translation table walks.
[19:16]
Reserved, RES0.
MaintBcst, [15:12]
Maintenance broadcast. Indicates whether cache, TLB and branch predictor operations are
broadcast:
B1 AArch32 system registers
B1.83 Memory Model Feature Register 3
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reserved.
B1-287
Non-Confidential