B1.77 Instruction Set Attribute Register 3
The ID_ISAR3 characteristics are:
Purpose
Provides information about the instruction sets implemented by the processor in AArch32.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RO RO RO RO RO
Must be interpreted with ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR4, and ID_ISAR5. See:
• B1.74 Instruction Set Attribute Register 0 on page B1-269
• B1.75 Instruction Set Attribute Register 1 on page B1-271
• B1.76 Instruction Set Attribute Register 2 on page B1-273
• B1.78 Instruction Set Attribute Register 4 on page B1-277
• B1.79 Instruction Set Attribute Register 5 on page B1-279
Configurations
ID_ISAR3 is architecturally mapped to AArch64 register ID_ISAR3_EL1. See B2.60 AArch32
Instruction Set Attribute Register 3, EL1 on page B2-461.
There is one copy of this register that is used in both Secure and Non-secure states.
Attributes
ID_ISAR3 is a 32-bit register.
TabBranch
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
ThumbCopy SVC SaturateThumbEE SynchPrim SIMDTrueNOP
Figure B1-32 ID_ISAR3 bit assignments
ThumbEE, [31:28]
Indicates the implemented Thumb Execution Environment (T32EE) instructions:
0x0 None implemented.
TrueNOP, [27:24]
Indicates support for True NOP instructions:
0x1 True NOP instructions in both the A32 and T32 instruction sets, and additional NOP-
compatible hints.
ThumbCopy, [23:20]
Indicates the support for T32 non flag-setting MOV instructions:
0x1 Support for T32 instruction set encoding T1 of the MOV (register) instruction, copying
from a low register to a low register.
TabBranch, [19:16]
Indicates the implemented Table Branch instructions in the T32 instruction set.
0x1 The TBB and TBH instructions.
B1 AArch32 system registers
B1.77 Instruction Set Attribute Register 3
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-275
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