0x2 The UMULL and UMLAL instructions.
The UMAAL instruction.
MultS, [19:16]
Indicates the implemented advanced signed Multiply instructions.
0x3 • The SMULL and SMLAL instructions.
• The SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT,
SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT instructions,
and the Q bit in the PSRs.
• The SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA,
SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX
instructions.
Mult, [15:12]
Indicates the implemented additional Multiply instructions:
0x2 The MUL instruction.
The MLA instruction.
The MLS instruction.
MultiAccessInt, [11:8]
Indicates the support for interruptible multi-access instructions:
0x0 No support. This means the LDM and STM instructions are not interruptible.
MemHint, [7:4]
Indicates the implemented memory hint instructions:
0x4 The PLD instruction.
The PLI instruction.
The PLDW instruction.
LoadStore, [3:0]
Indicates the implemented additional load/store instructions:
0x2 The LDRD and STRD instructions.
The Load Acquire (LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, and LDAEXD) and Store
Release (STLB, STLH, STL, STLEXB, STLEXH, STLEX, and STLEXD) instructions.
To access the ID_ISAR2:
MRC p15, 0, <Rt>, c0, c2, 2 ; Read ID_ISAR2 into Rt
Register access is encoded as follows:
Table B1-59 ID_ISAR2 access encoding
coproc opc1 CRn CRm opc2
1111 000 0000 0010 010
B1 AArch32 system registers
B1.76 Instruction Set Attribute Register 2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-274
Non-Confidential
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