B1.12 c9 registers
The processor can access different 32-bit wide system registers. Registers where CRn has the value nine
are called c9 registers.
The following table shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c9. See the Arm
®
Architecture Reference Manual Armv8, for
Armv8-A architecture profile for more information.
Table B1-12 c9 register summary CRn=c9
Op1 CRm Op2 Name Reset Description
0 c12 0 PMCR
0x410A3000
C10.6 Performance Monitors Control Register, EL0 on page C10-704
1 PMNCNTENSET UNK
Performance Monitors Count Enable Set Register
2 PMNCNTENCLR UNK
Performance Monitors Count Enable Clear Register
3 PMOVSR UNK
Performance Monitor Overflow Flag Status Clear Register
4 PMSWINC UNK
Performance Monitors Software Increment Register
5 PMSELR UNK
Performance Monitors Event Counter Selection Register
6 PMCEID0
0x6FFFBFFF
C10.3 Performance Monitors Common Event Identification Register 0
on page C10-695
The reset value is 0x6E3FBFFF if L2 cache is not implemented.
7 PMCEID1
0x00000000
C10.4 Performance Monitors Common Event Identification Register 1
on page C10-699
c13 0 PMCCNTR UNK
Performance Monitors Cycle Counter
1
PMXEVTYPER
UNK Performance Monitors Selected Event Type and Filter Register
2 PMXEVCNTR UNK Performance Monitors Selected Event Counter Register
c14 0 PMUSERENR
0x00000000
Performance Monitors User Enable Register
1 PMINTENSET UNK Performance Monitors Interrupt Enable Set Register
2 PMINTENCLR UNK
Performance Monitors Interrupt Enable Clear Register
3 PMOVSSET UNK
Performance Monitor Overflow Flag Status Set Register
1 c0 2 L2CTLR -
B1.92 L2 Control Register on page B1-303
The reset value depends on the processor configuration.
3 L2ECTLR
0x00000000
B1.93 L2 Extended Control Register on page B1-305
B1 AArch32 system registers
B1.12 c9 registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-167
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