B1.93 L2 Extended Control Register
The L2ECTLR characteristics are:
Purpose
Provides additional IMPLEMENTATION DEFINED control options for the L2 memory system. This
register is used for dynamically changing, but implementation specific, control bits.
Usage constraints
This register is accessible as follows:
EL0
(NS)
EL0
(S)
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - RW RW RW RW RW
The L2ECTLR can be written dynamically.
Configurations
L2ECTLR is mapped to the AArch64 L2ECTLR_EL1 register. See B2.75 L2 Extended Control
Register, EL1 on page B2-491.
There is one copy of this register that is used in both Secure and Non-secure states.
There is one L2ECTLR for the Cortex‑A35 processor.
Attributes
L2ECTLR is a 32-bit register.
31
0
30 28
RES0
RES0
29
L2 internal asynchronous error
123
AXI, ACE, or CHI asynchronous error L2 dynamic retention control
Figure B1-47 L2ECTLR bit assignments
[31]
Reserved, RES0.
L2 internal asynchronous error, [30]
L2 internal asynchronous error caused by L2 RAM double-bit ECC error. The possible values
are:
0 No pending asynchronous error. This is the reset value.
1 An asynchronous error has occurred.
A write of 0 clears this bit. A write of 1 is ignored.
AXI, ACE, or CHI asynchronous error, [29]
AXI, ACE, or CHI asynchronous error indication. The possible values are:
0 No pending asynchronous error.
1 An asynchronous error has occurred.
A write of 0 clears this bit. A write of 1 is ignored.
B1 AArch32 system registers
B1.93 L2 Extended Control Register
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
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B1-305
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