B2.45 Fault Address Register, EL2
The FAR_EL2 characteristics are:
Purpose
Holds the faulting Virtual Address for all synchronous instruction or data aborts, or exceptions
from a misaligned PC or a Watchpoint debug event, taken to EL2.
Usage constraints
This register is accessible as follows:
EL0
EL1
(NS)
EL1
(S)
EL2
EL3
(SCR.NS = 1)
EL3
(SCR.NS = 0)
- - - RW RW RW
Configurations
FAR_EL2[31:0] is architecturally mapped to AArch32 registers:
• HDFAR. See B1.64 Hyp Data Fault Address Register on page B1-251.
• DFAR (S). See B1.48 Data Fault Address Register on page B1-222.
FAR_EL2[63:32] is architecturally mapped to AArch32 registers:
• HIFAR. See B1.65 Hyp Instruction Fault Address Register on page B1-252.
• IFAR (S). See B1.86 Instruction Fault Address Register on page B1-293.
Attributes
FAR_EL2 is a 64-bit register.
VA
63 0
Figure B2-20 FAR_EL2 bit assignments
VA, [63:0]
The faulting Virtual Address for all synchronous instruction or data aborts, or an exception from
a misaligned PC, taken in EL2.
If a memory fault that sets the FAR is generated from one of the data cache instructions, this
field holds the address specified in the register argument of the instruction.
To access the FAR_EL2:
MRS <Xt>, FAR_EL2 ; Read EL2 Fault Address Register
MSR FAR_EL2, <Xt> ; Write EL2 Fault Address Register
Register access is encoded as follows:
Table B2-39 FAR_EL2 access encoding
op0 op1 CRn CRm op2
11 100 0110 0000 000
B2 AArch64 system registers
B2.45 Fault Address Register, EL2
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B2-430
Non-Confidential
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