B1.3 c1 registers
The processor can access different 32-bit wide system registers. Registers where CRn has the value one
are called c1 registers.
The following table shows the 32-bit wide system registers you can access when the processor is in
AArch32 state and the value of CRn is c1.
Table B1-3 c1 register summary
Op1 CRm Op2 Name Reset Description
0 c0 0 SCTLR
0x00C50838
B1.105 System Control Register on page B1-331
The reset value depends on inputs, CFGTE, CFGEND, and VINITHI. The value
listed here assumes these signals are set to LOW.
1 ACTLR
0x00000000
B1.32 Auxiliary Control Register on page B1-193
2 CPACR
0x00000000
B1.41 Architectural Feature Access Control Register on page B1-206
c1 0 SCR
0x00000000
B1.104 Secure Configuration Register on page B1-328
1 SDER
0x00000000
B1.107 Secure Debug Enable Register on page B1-337
2 NSACR
0x00000000
B1.98 Non-Secure Access Control Register on page B1-317
If EL3 is AArch64 then the NSACR reads as 0x00000C00.
c3 1 SDCR
0x00000000
B1.106 Secure Debug Control Register on page B1-335
4 c0 0 HSCTLR
0x03C50838
B1.67 Hyp System Control Register on page B1-254
1 HACTLR
0x00000000
B1.55 Hyp Auxiliary Control Register on page B1-231
c1 0 HCR
0x00000000
B1.61 Hyp Configuration Register on page B1-240
1 HDCR
0x00000006
B1.63 Hyp Debug Control Register on page B1-248
2 HCPTR
0x000033FF
B1.60 Hyp Architectural Feature Trap Register on page B1-237
The reset value depends on the FPU and NEON configuration. If Advanced SIMD and
floating-point are implemented, the reset value is 0x000033FF. If Advanced SIMD
and floating-point are not implemented, the reset value is 0x0000BFFF.
3 HSTR
0x00000000
B1.69 Hyp System Trap Register on page B1-259
4 HCR2
0x00000000
B1.62 Hyp Configuration Register 2 on page B1-246
7 HACR
0x00000000
B1.54 Hyp Auxiliary Configuration Register on page B1-230
B1 AArch32 system registers
B1.3 c1 registers
100236_0100_00_en Copyright © 2015–2017, 2019 Arm Limited or its affiliates. All rights
reserved.
B1-155
Non-Confidential
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