ARM Cortex-A35 User Manual

B2.9 AArch64 Miscellaneous operations
The following table shows the miscellaneous operations in AArch64 state.
See the Arm
®
Architecture Reference Manual Armv8, for Armv8-A architecture profile for more
information about these operations.
Table B2-9 AArch64 miscellaneous system operations
Name Type Reset Width Description
TPIDR_EL0 RW UNK 64
Thread Pointer / ID Register, EL0
TPIDR_EL1 RW UNK 64
Thread Pointer / ID Register, EL1
TPIDRRO_EL0
RW
RO at EL0.
UNK 64
Thread Pointer / ID Register, read-only, EL0
TPIDR_EL2 RW UNK 64
Thread Pointer / ID Register, EL2
TPIDR_EL3 RW UNK 64
Thread Pointer / ID Register, EL3
B2 AArch64 system registers
B2.9 AArch64 Miscellaneous operations
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ARM Cortex-A35 Specifications

General

Brand	ARM
Model	Cortex-A35
Category	Computer Hardware
Language	English